The present invention relates generally to network processors and, more particularly, to a processor architecture that may be useful in a network processor.
Communication systems are continually undergoing increased demands to process data at every increasing speeds. Accordingly, there is a need to provide processor architectures that can operate in communication systems at these increased speeds.
The present invention provides a processor architecture including a processor and local memory arrangement where the local memory may be accessed by the processor and other resources at substantially the same time. As a result, the processor may initiate a new or current process following a previous process without waiting for data or instructions from external resources. In addition, the loading of data for the next or subsequent process, the execution of a current process, and the extraction of results of a previous process can occur in parallel. Further, the processor may avoid memory load stall conditions because the processor does not have to access an external memory to execute the current process.
In another embodiment, the local memory may be dynamically reallocated so that results from a previous process stored in the local memory may be accessed by the processor for a current process without accessing an external memory.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.